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1 fn6813.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. femtocharge is a trademark of kenet inc. copyright intersil americas inc. 2008, 2011. all rights reserved all other trademarks mentioned are the property of their respective owners. kad2708l 8-bit, 350/275/210 /170/105msps a/d converter the intersil kad2708l is the industry?s lowest power, 8-bit, 350msps, high performance analog -to-digital converter. it is designed with intersil?s proprietary femtocharge? technology on a standard cmos process. the kad2708l offers high dynamic performance (48.8dbfs snr @ f in = 175mhz) while consuming less than 330mw. feat ures include an over-range indicator and a selectable divide-by-2 input clock divider. the kad2708l is one member of a pin-compatible family offering 8- and 10-bit adcs with sample rates from 105msps to 350msps and lvds-compatible or lvcmos outputs (table 1). this family of products is available in 68 ld rohs-compliant qfn packages with exposed paddle. performance is specified over the full industrial temperature range (-40c to +85c). features ? on-chip reference ? internal track and hold ?1.5v p-p differential input voltage ? 600mhz analog input bandwidth ? two?s complement or binary output ? over-range indicator ? selectable 2 clock divider ? lvds compatible outputs key specifications ? snr = 48.8dbfs at f s = 350msps, f in = 175mhz ? sfdr = 64dbc at f s = 350msps, f in = 175mhz ? power consumption < 330mw at f s = 350msps applications ? high-performance data acquisition ? portable oscilloscope ? medical imaging ? cable head ends ? power-amplifier linearization ? radar and satellite antenna array processing ? broadband communications ? point-to-point microwave systems ? communications test equipment pin-compatible family lvds drivers 1.21 v clock generation s/h inp inn 8-bit 350msps adc clk_p clk_n ovss avss avdd2 clkoutp clkoutn d7p ? d0p orp 2sc ovdd clkdiv + ? avdd3 vref vrefsel vcm 8 d7n ? d0n orn ordering information part number (notes 1, 2) speed (msps) temp. range (c) package pkg. dwg. # kad2708l-35q68 350 -40 to +85 68 ld qfn l68.10x10b kad2708l-27q68 275 -40 to +85 68 ld qfn l68.10x10b kad2708l-21q68 210 -40 to +85 68 ld qfn l68.10x10b KAD2708L-17q68 170 -40 to +85 68 ld qfn l68.10x10b kad2708l-10q68 105 -40 to +85 68 ld qfn l68.10x10b notes: 1. for moisture sensitivity lev el (msl), please see device information pages for kad2708l-10 , KAD2708L-17 , kad2708l-21 , kad2708l-27 , and kad2708l-35 . for more information on msl, please see tech brief tb363 . 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. table 1. pin-compatible products resolution, speed lvds ou tputs lvcmos outputs 8 bits 350msps kad2708l-35 10 bits 275msps kad2710l-27 kad2710c-27 8 bits 275msps kad2708l-27 kad2708c-27 10 bits 210msps kad2710l-21 kad2710c-21 8 bits 210msps kad2708l-21 kad2708c-21 10 bits 170msps kad2710l-17 kad2710c-17 8 bits 170msps KAD2708L-17 kad2708c-17 10 bits 105msps kad2710l-10 kad2710c-10 8 bits 105msps kad2708l-10 kad2708c-10 data sheet april 14, 2011
2 fn6813.1 april 14, 2011 table of contents absolute maximum ratings ........................................ 3 thermal information ..................................................... 3 electrical specifications ............................................... 3 digital specifications .................................................... 5 timing diagram ............................................................. 6 timing specifications .................................................. 6 esd ................................................................................ 6 pin description ............................................................. 7 pin configuration ......................................................... 8 typical performance curves .........................................9 functional description .................................................12 reset .........................................................................12 voltage reference .....................................................12 analog input ..............................................................12 clock input ............. .............. .............. .............. .........13 jitter ...........................................................................13 digital outputs ...........................................................14 equivalent circuits .......................................................14 layout considerations ................................................15 split ground and power planes ................................15 clock input considerations.... .............. .............. .........15 bypass and filtering ............. .............. .............. .........15 lvds outputs ...........................................................15 unused inputs ...........................................................15 definitions......................................................................15 package outline drawing ............................................16 l68.10x10b ................................................................16 kad2708l
3 fn6813.1 april 14, 2011 absolute maximum rati ngs thermal information avdd2 to avss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 2.1v avdd3 to avss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 3.7v ovdd2 to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 2.1v analog inputs to avss. . . . . . . . . . . . . . . . . -0.4v to avdd3 + 0.3v clock inputs to avss. . . . . . . . . . . . . . . . . . -0.4v to avdd2 + 0.3v logic inputs to avss (vrefsel, clkdiv) -0.4v to avdd3 + 0.3v logic inputs to ovss (rst, 2sc) . . . . . . . . -0.4v to ovdd2 + 0.3v vref to avss . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd3 + 0.3v analog output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma logic output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma lvds output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma thermal resistance (typical) ja (c/w) jc (c/w) 68 ld qfn package (notes 3, 4). . . . . 23 1.8 operating temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fea tures. see tech brief tb379 for details. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications all specifications apply under the fo llowing conditions unless otherwise noted: avdd2 = 1.8v, avdd3 = 3.3v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), f sample = 350msps, 270msps, 210msps, 170msps and 105msps, f in = nyquist at -0.5dbfs. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol conditions kad2708l-35 kad2708l-27 kad2708l-21 KAD2708L-17 kad2708l-10 units min (note 5) typ max (note 5) min (note 5) typ max (note 5) min (note 5) typ max (note 5) min (note 5) typ max (note 5) min (note 5) typ max (note 5) dc specifications analog input full-scale analog input range v fs 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 v p-p full scale range temp. drift a vtc full temp 257 230 210 198 176 ppm /c common- mode output voltage v cm 860 860 860 860 860 mv power requirements 1.8v analog supply voltage avdd2 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 3.3v analog supply voltage avdd3 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 1.8v analog supply current i avdd2 51 60 44 51 38 42 35 39 29 33 ma 3.3v analog supply current i avdd3 50 54 41 45 33 37 28 32 21 24 ma 1.8v digital supply current i ovdd 39 44 34 39 33 36 31 36 28 32 ma kad2708l
4 fn6813.1 april 14, 2011 power dissipation p d 327 365 275 310 237 263 211 241 172 196 mw ac specifications maximum conversion rate f s max 350 275 210 170 105 msps minimum conversion rate f s min 50 50 50 50 50 msps differential nonlinearity dnl f in = 10mhz (for -17 and -10 versions only) -0.3 0.2 0.4 -0.3 0.2 0.4 -0.3 0.2 0.4 -0.3 0.2 0.4 -0.3 0.2 0.4 lsb integral nonlinearity inl f in = 10mhz (for -17 and -10 versions only) -0.8 0.2 0.8 -0.8 0.2 0.8 -0.8 0.2 0.8 -0.8 0.2 0.8 -0.8 0.2 0.8 lsb signal-to- noise ratio snr f in = 10mhz 49.0 49.5 49.5 49.5 49.5 dbfs f in = nyquist 46.5 48.8 46.5 49.2 46.5 49.2 46.5 49.2 46.5 49.2 dbfs f in = 430mhz 48.0 49.0 49.1 49.1 49.1 dbfs signal-to- noise and distortion sinad f in = 10mhz 48.9 49.2 49.5 49.5 49.5 dbfs f in = nyquist 46.5 48.2 46.5 49.2 46.5 49.2 46.5 49.2 46.5 49.2 dbfs f in = 430mhz 47.7 48.9 48.9 49.0 48.9 dbfs effective number of bits enob f in = 10mhz 7.8 7.9 7.9 7.9 7.9 bits f in = nyquist 7.4 7.9 7.4 7.9 7.4 7.9 7.4 7.9 7.4 7.9 bits f in = 430mhz 7.6 7.8 7.8 7.8 7.8 bits spurious- free dynamic range sfdr f in = 10mhz 65.0 67.6 69.1 69.1 69.1 dbc f in = nyquist 61 64 61 66.6 61 69.1 61 69.1 61 69.1 dbc f in = 430mhz 62 66.1 69.0 69.0 68.9 dbc two-tone sfdr 2tsfdr f in = 133mhz, 135mhz 61 63 65 65 65 dbc word error rate wer 10 -12 10 -12 10 -12 10 -12 10 -12 full power bandwidth fpbw 600 600 600 600 600 mhz note: 5. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications all specifications apply under the fo llowing conditions unless otherwise noted: avdd2 = 1.8v, avdd3 = 3.3v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), f sample = 350msps, 270msps, 210msps, 170msps and 105msps, f in = nyquist at -0.5dbfs. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol conditions kad2708l-35 kad2708l-27 kad2708l-21 KAD2708L-17 kad2708l-10 units min (note 5) typ max (note 5) min (note 5) typ max (note 5) min (note 5) typ max (note 5) min (note 5) typ max (note 5) min (note 5) typ max (note 5) kad2708l
5 fn6813.1 april 14, 2011 digital specifications parameter symbol conditions min (note 5) typ max (note 5) units inputs high input voltage (vrefsel) vrefsel v ih 0.8*avdd3 v low input voltage (vrefsel) vrefsel v il 0.2*avdd3 v input current high (vrefsel) vrefsel i ih v in = avdd3 0 1 10 a input current low (vrefsel) vrefsel i il v in = avss 25 65 75 a high input voltage (clkdiv) clkdiv v ih 0.8*avdd3 v low input voltage (clkdiv) clkdiv v il 0.2*avdd3 v input current high (clkdiv) clkdiv i ih v in = avdd3 256575a input current low (clkdiv) clkdiv i il v in = avss 0 1 10 a high input voltage (rst,2sc) rst,2sc v ih 0.8*ovdd2 v low input voltage (rst,2sc) rst,2sc v il 0.2*ovdd2 v input current high (rst,2sc) rst,2sc i ih vin = ovdd 0 1 10 a input current low (rst,2sc) rst,2sc i il vin = ovss 25 50 75 a input capacitance c di 3pf clkp, clkn p-p differential input voltage v cdi 0.5 3.6 v p-p clkp, clkn differential input resistance r cdi 10 m clkp, clkn common-mode input voltage v cci 0.9 v lvds outputs differential output voltage v t 210 mv output offset voltage v os 1.15 v output rise time t r 500 ps output fall time t f 500 ps kad2708l
6 fn6813.1 april 14, 2011 esd electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. industry-standard protection techniques have been utilized in the design of this product. however, reasonable care must be taken in the storage and handling of esd sensitive products. contact in tersil for the specific esd sensitivity rating of this product. timing diagram figure 1. lvds timing diagram inp inn clkp clkn clkoutp clkoutn d[7:0]n d[7:0]p t a t pid t pcd data n-l l sample n data n invalid t ph data n-l+1 timing specifications parameter symbol min typ max units aperture delay t a 1.7 ns rms aperture jitter j a 200 fs input clock to data propagation delay t pid 3.5 5.0 6.5 ns data hold time t ph -300 ps output clock to data propagation delay t pcd 2.8 3.7 ns latency (pipeline delay) l 28 cycles overvoltage recovery t ovr 1cycle kad2708l
7 fn6813.1 april 14, 2011 pin description pin number name function 1, 14, 18, 20 avdd2 1.8v analog supply 2, 7, 10, 19, 21, 24 avss analog supply return 3 vref reference voltage out/in 4 vrefsel reference voltage select (0:int 1:ext) 5 vcm common-mode voltage output 6, 15, 16, 25 avdd3 3.3v analog supply 8, 9 inp, inn analog input positive, negative 11-13, 29-36, 62, 63, 67 dnc do not connect 17 clkdiv clock divide by two (active low) 22, 23 clkn, clkp clock input complement, true 26, 45, 61 ovss output supply return 27, 41, 44, 60 ovdd2 1.8v lvds supply 28 rst power on reset (active low) 37, 38 d0n, d0p lvds bit 0 (lsb) output complement, true 39, 40 d1n, d1p lvds bit 1 output complement, true 42, 43 clkoutn, clkoutp lvds clock output complement, true 46, 47 d2n, d2p lvds bit 2 output complement, true 48, 49 d3n, d3p lvds bit 3 output complement, true 50, 51 d4n, d4p lvds bit 4 output complement, true 52, 53 d5n, d5p lvds bit 5 output complement, true 54, 55 d6n, d6p lvds bit 6 output complement, true 56, 57 d7n, d7p lvds bit 7 output complement, true 58, 59 orn, orp over-range complement, true 64-66 connect to ovdd2 68 2sc two?s complement select (active low) exposed paddle avss analog supply return kad2708l
8 fn6813.1 april 14, 2011 pin configuration 2sc dnc ovdd2 ovdd2 ovdd2 dnc dnc ovss ovdd2 orp orn d7p d7n d6p d6n d5p d5n avdd2 avss avdd2 avss clkn clkp avss avdd3 ovss ovdd2 rst dnc dnc dnc dnc dnc dnc avdd2 avss vref vrefsel vcm avdd3 avss inp inn avss dnc dnc dnc avdd2 avdd3 avdd3 clkdiv kad2708l top view not to scale d2p d2n ovss ovdd2 clkoutp clkoutn ovdd2 d1p d1n d0p d0n dnc dnc d4p d4n d3p d3n 68 qfn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 figure 2. pin configuration kad2708l
9 fn6813.1 april 14, 2011 typical performance curves avdd2 = ovdd2 = 1.8v, avdd3 = 3.3v, t a = +25c, f sample = 350mhz, f in = 175mhz, a in = -0.5dbfs unless noted. figure 3. snr and sfdr vs f in figure 4. hd2 and hd3 vs f in figure 5. snr and sfdr vs a in figure 6. hd2 and hd3 vs a in figure 7. snr and sfdr vs f sample figure 8. hd2 and hd3 vs f sample 40 45 50 55 60 65 70 5 105 205 305 405 505 f in (m hz) snr(dbfs), sfdr(d b sfdr snr bc) -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 5 205 3 05 405 505 f in (mhz) hd 2, hd3(db c hd3 hd2 (dbc) 20 30 40 50 60 70 80 -30 -25 -20 -15 -10 -5 0 a in (dbfs ) snr (dbfs), sfdr ( d sfdr snr (dbc) -80 -70 -60 -50 -40 -30 -20 -30 -25 -20 -15 -10 -5 0 input amplitude (dbfs) hd2, hd3 dbc hd3 hd2 (dbc) 40 44 48 52 56 60 64 68 72 76 80 50 100 150 200 250 300 350 f sa mp le (f s ) (msps) snr(dbfs), sfdr (dbc) sfdr snr -90 -85 -80 -75 -70 -65 50 100 150 200 250 300 350 f sample (msps) hd2, hd3(dbc) hd3 hd2 kad2708l
10 fn6813.1 april 14, 2011 figure 9. power dissipation vs f sample figure 10. differential nonlinearity vs output code figure 11. integral nonlinearity vs output code figure 12. noise histogram figure 13. output spectrum @ 9.865mhz figure 14. output spectrum @ 133.805mhz typical performance curves avdd2 = ovdd2 = 1.8v, avdd3 = 3.3v, t a = +25c, f sample = 350mhz, f in = 175mhz, a in = -0.5dbfs unless noted. (continued) 15 0 17 0 19 0 210 230 250 270 290 310 330 350 100 150 200 250 300 350 f sample (f s ) (msps) power dissipation (p d ) (mw) 0 32 64 96 128 160 192 224 255 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 code dnl (lsbs) 0 32 64 96 128 160 192 224 25 5 -1 -0.7 5 -0.5 -0.2 5 0 0.2 5 0.5 0.7 5 1 code inl (lsbs) 124 125 126 12 7 128 129 130 0 5,00 0 10,000 15,000 20,000 25,000 30,000 35,000 40,000 45,000 50,000 code code c oun t 0 20 40 60 80 100 120 -1 2 0 -1 0 0 -80 -60 -40 -20 0 f requency (mhz) amplitude (db) ain = -0.47dbfs snr = 49.4dbfs sfdr = 68.4dbc sinad = 49.3dbfs hd2 = -86dbc hd3 = -69dbc 0 20 40 60 80 100 120 -120 -100 -8 0 -6 0 -4 0 -2 0 0 frequency (mhz) amplitude (db) ain = -0.47dbfs snr = 49.4dbfs sfdr = 69.2dbc sinad = 49.4dbfs hd2 = -81dbc hd3 = -91dbc kad2708l
11 fn6813.1 april 14, 2011 figure 15. output spectrum @ 299.645mhz fig ure 16. two-tone spectrum @ 69mhz, 70mhz figure 17. two-tone spectrum @ 140mhz, 141mhz fi gure 18. two-tone spectrum @ 300mhz, 305mhz figure 19. snr and sfdr vs temperature figure 20. calibration time vs f s typical performance curves avdd2 = ovdd2 = 1.8v, avdd3 = 3.3v, t a = +25c, f sample = 350mhz, f in = 175mhz, a in = -0.5dbfs unless noted. (continued) 0 20 40 60 80 10 0 12 0 -120 -100 -8 0 -6 0 -4 0 -2 0 0 f r e que n c y ( m hz ) ampl itude (db ) ain = -0.48dbfs snr = 49.3dbfs sfdr = 63dbc sinad = 49.1dbfs hd2 = -63dbc hd3 = -67dbc 0 20 40 60 80 100 120 -1 20 -1 00 -80 -60 -40 -20 0 frequency (mhz) amplitude (db) ain = -7.1dbfs 2tsfdr = 67dbc imd3 = -74db fs 0 20 40 60 80 100 12 0 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (db) ain = -7dbfs 2tsfdr = 73dbc imd3 = -81d b fs 0 20 40 60 80 10 0 120 -1 20 -1 00 -80 -60 -40 -20 0 frequency (mhz) amplitude (db) ain = -7d bfs 2tsfd r = 63 db c im d 3 = - 7 6 db f s 40 45 50 55 60 65 70 75 -40 -20 0 20 40 60 80 ambient temperature, c snr(dbfs), sfdr(dbc ) sfdr snr 100 200 300 400 500 600 700 100 125 150 175 200 225 250 275 300 325 350 f sample (f s ) (msps) t cal (ms) kad2708l
12 fn6813.1 april 14, 2011 functional description the kad2708l is an 8-bit, 350msps a/d converter in a pipelined architecture. the input voltage is captured by a sample-and-hold circuit and converted to a unit of charge. proprietary charge-domain techniques are used to compare the input to a series of reference charges. these comparisons determine the digital code for each input value. the converter pipeline requires 24 sample clocks to produce a result. digital error correction is also applied, resulting in a total latency of 28 clock cycles. th is is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. at start-up, a self-calibration is performed to minimize gain and offset errors. the reset pin (rst) is initially held low internally at power-up and remains in that state until calibration is complete. the clock frequency should remain fixed during this time. calibration accuracy is maintained for the sample rate at which it is performed and theref ore should be repeated if the clock frequency is changed by more than 10%. recalibration can be initiated via the rst pin, or power cycling, at any time. reset recalibration of the adc can be initiated at any time by driving the rst pin low for a mi nimum of one clock cycle. an open-drain driver is recommended. the calibration sequence is initiated on the rising edge of rst, as shown in figure 21. the over-ra nge output (orp) is set high once rst is pulled low, and it remains in that state until calibration is complete. the orp output returns to normal operation at that time, so it is important that the analog input be within the converter?s full-scale range in order to observe the transition. if the input is in an over-range state, the orp pin stays high, and it is not possible to detect the en d of the calibration cycle. while rst is low, the output clock (clkoutp/clkoutn) stops toggling and is set low. normal operation of the output clock resumes at the next input clock edge (clkp/clkn) after rst is deasserted. at 350msps, the nominal calibration time is ~190ms. voltage reference the vref pin is the full-scale reference, which sets the full-scale input voltage for the chip and requires a bypass capacitor of 0.1f or larger. an internally generated reference voltage is provided from a bandgap voltage buffer. this buffer can sink or source up to 50a externally. an external voltage can be applied to this pin to provide a more accurate reference than the internally generated bandgap voltage or to match the full-scale reference among a system of kad2708l chips. one option in the latter configuration is to use one kad2708l's internally generated reference as the external reference voltage for the other chips in the system. additionally, an externally provided reference can be changed from the nominal value to adjust the full-scale input voltage within a limited range. to select whether the full-scale reference is internally generated or externally prov ided, the digital input port, vrefsel, should be set appropriately: low for internal, or high for external. this pin also has an internal 18k pull-up resistor. to use the internally generated reference, vrefsel can be tied directly to avss, and to use an external reference, vrefsel can be left unconnected. analog input the fully differential adc input (inp/inn) connects to the sample-and-hold circuit. the ideal full-scale input voltage is 1.5v p-p , centered at the vcm voltage of 0.86v, as shown in figure 22. best performance is obtained when the analog inputs are driven differentially. the co mmon-mode output voltage, vcm, should be used to properly bias each input, as shown in figures 23 and 24. an rf transformer gives the best noise and distortion performance for wideband and/or high intermediate frequency (if) input s. two different transformer input schemes are shown in figures 23 and 24. figure 21. calibration timing clkp clkn clkoutp rst orp calibration begins calibration complete calibration time figure 22. analog input range 1.0 1.8 0.6 0.2 1.4 inp inn vcm 0.86v 0.75v -0.75v v t kad2708l
13 fn6813.1 april 14, 2011 a back-to-back transformer scheme is used to improve common-mode rejection, wh ich keeps the common-mode level of the input matched to v cm . the value of the termination resistor should be determined based on the desired impedance. the sample-and-hold circuit design uses a switched capacitor input stage, which creates current spikes when the sampling capacitance is reconnected to the input voltage. this creates a disturbance at the input, which must settle before the next sampling point. lower source impedance results in faster settling and improved performance; therefore, a 1:1 transformer and low shunt resistance are recommended for optimal performance. a differential amplifier can be used in applications that require dc coupling, at the expense of reduced dynamic performance. in this configuration, the amplifier typically reduces the achievable snr and distortion performance. a typical differential amplifier configuration is shown in figure 25. clock input the clock input circuit is a differential pair (figure 29). driving these inputs with a high level (up to 1.8v p-p on each input) sine or square wave provides the lowest jitter performance. the recommended drive circuit is shown in figure 26. the clock can be driven single-ended, but this reduces the edge rate and may impact snr performance. use of the clock divider is optional. the kad2708l's adc requires a clock with 50% duty cycle for optimum performance. if such a clock is not available, one option is to generate twice the desired sampling rate, and then use the kad2708l's divide-by-2 to generate a 50%-duty-cycle clock. this frequency divider uses the rising edge of the clock, so a 50% clock duty cycle is assu red. table 2 describes the clkdiv connection. clkdiv is internally pulled low, so a pull-up resistor or logic driver must be connected for undivided clock. jitter in a sampled data system, clock jitter directly impacts the achievable snr performance. the theoretical relationship between clock jitter and maximum snr is shown in equation 1 and illustrated in figure 27. where t j is the rms uncertainty in the sampling instant. this relationship shows the snr that would be achieved if clock jitter were the only non-ideal factor. in reality, achievable snr is limited by internal factors such as differential nonlinearity aperture jitter and thermal noise. figure 23. transformer input, general application adt1-1wt 0.1f kad2708 vcm 50 o 0.01f analog in adt1-1wt adtl1-12 0.1f kad2708 vcm adtl1-12 1nf 1nf analog input 25 o 25 o figure 24. transformer input, high if application kad2708 vcm 0.1f 0.22f 69.8o 49.9o 100o 100o 69.8o 348o 348o cm 151o 25o 25o + vin - figure 25. differential amplifier input table 2. clkdiv pin settings clkdiv pin divide ratio avss 2 avdd 1 tc4-1w 1nf avdd2 200o clkp clkn 1ko 1ko 1nf clock input figure 26. recommended clock drive snr 20 log 10 1 2 f in t j ------------------- - ?? ?? = (eq. 1) kad2708l
14 fn6813.1 april 14, 2011 any internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, si nce they are not statistically correlated, and this determines the tota l jitter in the system. the total jitter, combined with other noise sources, then determines the achievable snr. digital outputs data is output on a parallel bus with lvds-compatible drivers. the output format (binary or tw o?s complement) is selected via the 2sc pin as shown in table 3. tj = 1 00 p s tj = 10 p s tj = 1 p s tj = 0. 1 p s 10 bits 12 bi ts 14 bi ts 50 55 60 65 70 75 80 85 90 95 10 0 1101001000 in put fr equen cy - mh z snr - d b figure 27. snr vs clock jitter table 3. 2sc pin settings 2sc pin mode avss two?s complement avdd (or unconnected) binary equivalent circuits figure 28. analog inputs figure 29. clock inputs figure 30. lvds outputs avdd3 inp inn avdd3 f1 f1 f2 csamp 0.3pf to charge pipeline 2pf f2 csamp 0.3pf to charge pipeline avdd2 clkp clkn avdd2 avdd2 to clock generation d[7:0]p ovdd ovdd data data data data d[7:0]n ovdd kad2708l
15 fn6813.1 april 14, 2011 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com layout considerations split ground and power planes data converters operating at high sampling frequencies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. ground planes, if separated, should be joined at the exposed paddle under the chip. clock input considerations use matched transmission lines to the inputs for the analog input and clock signals. locate transformers, drivers and terminations as close to the chip as possible. bypass and filtering bulk capacitors should have low equivalent series resistance. tantalum is a good choice. for best performance, keep ceramic bypass capacitors very close to device pins. longer traces increase inductance, re sulting in diminished dynamic performance and accuracy. make sure that connections to ground are direct and low impedance. lvds outputs output traces and connections must be designed for 50 (100 differential) characteristic impedance. keep traces direct, and minimize bends where possible. avoid crossing ground and power-plane breaks with signal traces. unused inputs the rst and 2sc inputs are internally pulled up and can be left open-circuit if not used. clkdiv is internally pulled low, which divides the input clock by two. vrefsel is internally pulled up. it must be held low for internal reference, but it can be left open for external reference. definitions analog input bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by fft analysis) is reduced by 3db from its full-scale, low-fr equency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time required after the rise of the clock in put for the sampling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non- linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-distortion ratio (sinad). in db, it is calculated as: enob = (sinad - 1.76)/6.02. integral non-linearity (inl) is the deviation of each individual code from a line drawn from n egative full-scale (1/2 lsb below the first code transition) through positive full-scale (1/2 lsb above the last code transition). the deviation of any given code from this line is measured from the center of that code. least significant bit (lsb) is the bit that has the smallest value or weight in a digital word. its value in terms of input voltage is vfs/(2n-1) where n is the resolution in bits. missing codes are output codes that are skipped and never appear at the adc output. th ese codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. its value in terms of input voltage is vfs/2. pipeline delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the corresponding data. power supply rejection ratio (psrr) is the ratio of a change in power supply voltage to the input voltage necessary to negate the resu ltant change in output code. signal to noise-an d-distortion (sinad) is the ratio of the rms signal amplitude to the rm s sum of all other spectral components below one-half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (snr) (without harmonics) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one-half the sampling frequency, excluding harmonics and dc. spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious spectral component may or may not be a harmonic. two-tone sfdr is the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. kad2708l
16 fn6813.1 april 14, 2011 kad2708l package outline drawing l68.10x10b 68 lead quad flat no-lead plastic package rev 0, 11/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 i dentifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancin g conform to amsey14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view bottom view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 b 6 pin 1 index area 17 1 34 18 0.10 a mc b 4 a 4x 8.00 68x 0.55 68x 0.25 64x 0.50 10.00 10.00 0.90 max 68x 0.25 68x 0.75 64x 0.50 7.70 sq 9.65 sq 6 pin 1 index area exp. dap 7.70 sq. see detail "x" seating plane 0.08 0.10 c c c 8.00 sq (4x) 0.15 35 51 52 68

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